Oral Presentation
Feasibility Study on Integrated Multi-Pixel Heterodyne Receiver Chip and Module working at 220 GHz
Presenter: Ming-Jye Wang (ASIAA)
The quick development of the sensitive receiver based on superconductor detector technology makes the astronomical researches on sub-mm wavelength grow enormously in the past three decades. Many telescopes with different instruments working on sub-mm wavelengths were built for targeting different astronomical topics. The cost of a telescope is extremely high, typically >10M USD and could be more than 500M USD for a next generation large aperture (50-m class) sub-mm telescope. Enhancement of the observation speed is a very important issue for the operation of the telescope. Multi-pixel receiver is one of the solutions. Because of a complicated system in heterodyne detection, nowadays, only a few multi-pixel sub-mm wavelength heterodyne receivers were deployed on the telescopes. However, the receiver system based on current architecture is difficult to achieve a large number of pixels (>100). An integrated multi-pixel sub-mm wavelength receiver chip definitely is a critical technology for next generation multi-pixel sub-mm wavelength heterodyne receiver, which is not realized yet.
We are studying the feasibility of constructing a compact 7-pixel receiver module working at 230 GHz based on integrated sub-millimeter wave circuits on single integrated receiver chip, especially on developing the necessary key technologies. To simplify the structure at the proof-of-concept stage, each pixel is of single polarization and double-side-band (DSB) detection. The receiver chip consists of planar RF (LO) probes, planar LO power distributor, planar LO/RF couplers, RF impedance matching circuits, SIS mixers, CPW (co-planar waveguide) IF output ports, and DC wires for SIS mixer bias and control lines. Seven conical horns are arranged in hexagonal configuration in the front size to couple the signal from sky. A single LO source is injected from the backside. The receiver chip is embedded in the housing with waveguide input ports, IF output connectors, SIS mixer DC bias and control lines. The conceptual design and also current progress will be presented.
asiaa.sinica.edu.tw